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Disambiguation of "Ishihara, Tohru"

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A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors.

, and . DATE, page 617-623. IEEE Computer Society / ACM, (2000)

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Tohru Iwai

Aeka Ishihara

Hirofumi Ishihara

 

Other publications of authors with the same name

DLIC: Decoded loop instructions caching for energy-aware embedded processors., , and . ACM Trans. Embed. Comput. Syst., 13 (1): 6:1-6:26 (2013)Message from the Editor-in-Chief.. IPSJ Trans. Syst. LSI Des. Methodol., (2024)Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring., , , and . IEEE J. Solid State Circuits, 50 (11): 2475-2490 (2015)An energy-efficient on-chip memory structure for variability-aware near-threshold operation., , and . ISQED, page 23-28. IEEE, (2015)Virtualizing DVFS for Energy Minimization of Embedded Dual-OS Platform., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 107 (1): 3-15 (January 2024)Identification of Redundant Flip-Flops Using Fault Injection for Low-Power Approximate Computing Circuits., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 107 (3): 540-548 (2024)A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 100-A (12): 2764-2775 (2017)Analytical Stability Modeling for CMOS Latches in Low Voltage Operation., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 99-A (12): 2463-2472 (2016)Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (12): 2499-2507 (2013)Performance Modeling of VIA-Switch FPGA for Device-Circuit-Architecture Co-Optimization., , and . SoCC, page 112-117. IEEE, (2018)