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Flip-Flop and Repeater Insertion for Early Interconnect Planning.

, , , and . DATE, page 690-695. IEEE Computer Society, (2002)

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A high performance bus communication architecture through bus splitting., and . ASP-DAC, page 751-755. IEEE Computer Society, (2004)Postlayout optimization for synthesis of Domino circuits., , , and . ACM Trans. Design Autom. Electr. Syst., 11 (4): 797-821 (2006)Flip-Flop and Repeater Insertion for Early Interconnect Planning., , , and . DATE, page 690-695. IEEE Computer Society, (2002)Improving the scalability of SAMBA bus architecture., , and . ASP-DAC, page 1164-1167. ACM Press, (2005)SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips., , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (1): 69-79 (2007)SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips., and . ICCAD, page 8-12. IEEE Computer Society / ACM, (2003)Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels., and . ICCAD, page 227-231. IEEE Computer Society / ACM, (2003)Post-layout logic duplication for synthesis of domino circuits with complex gates., , and . ASP-DAC, page 260-265. ACM Press, (2005)Interconnect Planning with Local Area Constrained Retiming., and . DATE, page 10442-10447. IEEE Computer Society, (2003)Performance analysis of latency-insensitive systems., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (3): 469-483 (2006)