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Disambiguation of "Nonis, Roberto"

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Design of a 8-taps, 10Gbps transmitter for automotive micro-controllers.

, , , , and . APCCAS, page 321-324. IEEE, (2016)

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Fabián David Nonis

Roberto Klimmek

Roberto Ohrt

Roberto Cattaneo

Roberto Menegazzo

 

Other publications of authors with the same name

A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion., , , , , and . ESSCIRC, page 45-48. IEEE, (2019)A Time-Domain Simulation Framework for the Modeling of Jitter in High-Speed Serial Interfaces., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (2): 940-951 (February 2023)Modeling and design of low power integrated circuits for frequency synthesis in CMOS technology.. University of Udine, Italy, (2007)Modeling, design and characterization of a new low jitter analog dual tuning LC-VCO PLL architecture., , , and . ISCAS (4), page 553-556. IEEE, (2004)Low noise active loop filter for radar PLL applications., , , and . ICICDT, page 77-80. IEEE, (2018)A Design Methodology for MOS Current-Mode Logic Frequency Dividers., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 54-I (2): 245-254 (2007)F2: High-performance frequency generation for wireless and wireline systems., , , , , and . ISSCC, page 503-505. IEEE, (2017)A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider., , , , and . ISSCC, page 356-357. IEEE, (2013)Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (6): 1628-1638 (2008)Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 67-II (8): 1369-1373 (2020)