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Disambiguation of "Chattopadhyay, Anupam"

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RunFein: a rapid prototyping framework for Feistel and SPN-based block ciphers.

, , , and . J. Cryptogr. Eng., 6 (4): 299-323 (2016)

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Anupam Chattopadhyay

Anupam Singh

Anupam Karmakar

Anupam Sengupta

Dhrupadi Chattopadhyay

 

Other publications of authors with the same name

Crack me if you can: hardware acceleration bridging the gap between practical and theoretical cryptanalysis?: a Survey., , , and . SAMOS, page 167-172. ACM, (2018)Accelerating Binary-Matrix Multiplication on FPGA., , and . SoCC, page 254-259. IEEE, (2019)Trace Buffer Attack: Security versus observability study in post-silicon debug., , and . VLSI-SoC, page 355-360. IEEE, (2015)Lattice-based Key Sharing Schemes - A Survey., , , and . IACR Cryptol. ePrint Arch., (2020)Constructive Reversible Logic Synthesis for Boolean Functions with Special Properties., , , and . RC, volume 8507 of Lecture Notes in Computer Science, page 95-110. Springer, (2014)Cryptanalysis of the Double-Feedback XOR-Chain Scheme Proposed in Indocrypt 2013., , and . INDOCRYPT, volume 8885 of Lecture Notes in Computer Science, page 179-196. Springer, (2014)System-level reliability exploration framework for heterogeneous MPSoC., , , and . ACM Great Lakes Symposium on VLSI, page 9-14. ACM, (2014)Designing stream ciphers with scalable data-widths: a case study with HC-128., and . J. Cryptographic Engineering, 4 (2): 135-143 (2014)Three Snakes in One Hole: The First Systematic Hardware Accelerator Design for SOSEMANUK with Optional Serpent and SNOW 2.0 Modes., and . IEEE Trans. Computers, 65 (2): 640-653 (2016)Complexity Analysis of Reversible Logic Synthesis., , and . CoRR, (2014)