( en | de | ru )

 

Disambiguation of "Chen, Mike Shuo-Wei"

Author of the publication

copydeleteadd this publication to your clipboard
A 12 bit 1 GS/s Dual-Rate Hybrid DAC With an 8 GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving > 75 dB SFDR Over the Nyquist Band.

, , , and . IEEE J. Solid State Circuits, 50 (4): 896-907 (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Wei Chen

Wei Chen

Wei Chen

Wei Chen

Wei Chen

 

Other publications of authors with the same name

Novel Radio Architectures for UWB, 60 GHz, and Cognitive Wireless Systems., , , , , and . EURASIP J. Wireless Comm. and Networking, (2006)Impact of Sampling Jitter on Mostly-Digital Architectures for UWB Bio-Medical Applications., , , , , and . ICC, page 5769-5774. IEEE, (2007)A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS., and . ISSCC, page 394-396. IEEE, (2018)16.7 A 40MHz-BW 76.2dB/78.0dB SNDR/DR Noise-Shaping Nonuniform Sampling ADC with Single Phase-Domain Level Crossing and Embedded Nonuniform Digital Signal Processor in 28nm CMOS., and . ISSCC, page 262-264. IEEE, (2020)27.1 A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error pre-distortion and in-band noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS., and . ISSCC, page 456-457. IEEE, (2016)A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation., , , and . IEEE J. Solid State Circuits, 53 (6): 1765-1779 (2018)A Digital PLL With Feedforward Multi-Tone Spur Cancellation Scheme Achieving <-73 dBc Fractional Spur and <-110 dBc Reference Spur in 65 nm CMOS., and . IEEE J. Solid State Circuits, 51 (12): 3216-3230 (2016)Design and implementation of a CMO 802.11n SoC., , , , , , , , , and 18 other author(s). IEEE Commun. Mag., 47 (4): 134-143 (2009)Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms., , , , , and . ASP-DAC, page 100-107. IEEE, (2022)A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis., , and . ACM Trans. Design Autom. Electr. Syst., 26 (5): 38:1-38:22 (2021)