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Disambiguation of "Chang, Meng-Fan"

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A nonvolatile look-up table using ReRAM for reconfigurable logic.

, , , , , , , , , , , , , , , , and . A-SSCC, page 133-136. IEEE, (2014)

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Fan Chen Meng

Meng-Chang Liu

Meng Meng

Meng Meng Liang

Meng Zhang

Methods and implementations of road-network matching. TU München, (2009)
 

Other publications of authors with the same name

A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques., , , , , , , , , and 2 other author(s). VLSIC, page 112-113. IEEE, (2012)A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors., , , , , , , , , and 7 other author(s). ISSCC, page 494-496. IEEE, (2018)A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 59 (1): 116-127 (January 2024)A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme., , , , , , , , , and . IEEE J. Solid State Circuits, 46 (4): 815-827 (2011)A 0.8 V Intelligent Vision Sensor With Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification., , , , , , , and . IEEE J. Solid State Circuits, 58 (11): 3266-3274 (November 2023)A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 59 (1): 52-64 (January 2024)A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 52 (8): 2194-2207 (2017)A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 52 (10): 2769-2785 (2017)A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 56 (5): 1641-1650 (2021)A Full-Sensing-Margin Dual-Reference Sensing Scheme for Deeply-Scaled STT-RAM., , , , and . IEEE Access, (2018)