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Disambiguation of "Jung, Dong-Hoon"

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All-Digital ON-Chip Process Sensor Using Ratioed Inverter-Based Ring Oscillator.

, , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (11): 3232-3242 (2016)

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Dong-Hoon Han

Dong-Hoon Kim

Dong-Hoon Lee

Dong-Hoon Won

Jung-Hoon Lee

 

Other publications of authors with the same name

All-Digital Process-Variation-Calibrated Timing Generator for ATE With 1.95-ps Resolution and Maximum 1.2-GHz Test Rate., , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (6): 1015-1025 (2018)ADDLL for Clock-Deskew Buffer in High-Performance SoCs., , , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (7): 1368-1373 (2013)GRO-TDC with gate-switch-based delay cell halving resolution limit., , and . Int. J. Circuit Theory Appl., 45 (12): 2211-2225 (2017)14.6 A 10A Computational Digital LDO Achieving 263A/mm2 Current Density with Distributed Power-Gating Switches and Time-Based Fast-Transient Controller for Mobile SoC Application in 3nm GAAFET., , , , , , and . ISSCC, page 264-266. IEEE, (2024)29.6 A Distributed Digital LDO with Time-Multiplexing Calibration Loop Achieving 40A/mm2 Current Density and 1mA-to-6.4A Ultra-Wide Load Range in 5nm FinFET CMOS., , , , , , , and . ISSCC, page 414-416. IEEE, (2021)Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (3): 413-421 (2015)All-Digital 90° Phase-Shift DLL With Dithering Jitter Suppression Scheme., , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (3): 1015-1024 (2016)Process Variation Tolerant All-Digital 90° Phase Shift DLL for DDR3 Interface., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (10): 2186-2196 (2012)All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate., , and . ESSCIRC, page 41-44. IEEE, (2013)Lessons Learned from an Auditory-vibrotactile Sensory Experience in the Museum., , , , and . ISS, page 373-378. ACM, (2019)