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Synthesizable-from-C Embedded Processor Based on MIPS-ISA and OISC.

, , , and . EUC, page 114-123. IEEE Computer Society, (2015)

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FPGA glitch power analysis and reduction., and . ISLPED, page 27-32. IEEE/ACM, (2011)EASY: Efficient Arbiter SYnthesis from Multi-threaded Code., , , , and . FPGA, page 142-151. ACM, (2019)From software threads to parallel hardware in high-level synthesis for FPGAs., , and . FPT, page 270-277. IEEE, (2013)Preface., , , , and . FPL, page 1. IEEE, (2016)A Dynamic Memory Allocation Library for High-Level Synthesis., and . FPL, page 314-320. IEEE, (2019)Packing Techniques for Virtex-5 FPGAs., , and . ACM Trans. Reconfigurable Technol. Syst., 2 (3): 18:1-18:24 (2009)VTR 7.0: Next Generation Architecture and CAD System for FPGAs., , , , , , , , , and 4 other author(s). ACM Trans. Reconfigurable Technol. Syst., 7 (2): 6:1-6:30 (2014)The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware., , , , , , , and . ACM Trans. Reconfigurable Technol. Syst., 8 (3): 14:1-14:26 (2015)Subleq⊝: An Area-Efficient Two-Instruction-Set Computer., , , and . IEEE Embed. Syst. Lett., 9 (2): 33-36 (2017)FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (9): 1305-1318 (2012)