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Evaluating shared virtual memory in an OpenCL framework for embedded systems on FPGAs.

, and . ReConFig, page 1-8. IEEE, (2015)

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The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System., , , , and . FPGA, page 53-61. ACM, (1997)Enabling network function virtualization over heterogeneous resources., , , , and . APNOMS, page 58-63. IEEE, (2017)NetThreads-10G: Software packet processing on NetFPGA-10G in a virtualized networking environment demonstration abstract., , and . FPL, page 1. IEEE, (2013)RACER: a reconfigurable constraint-length 14 Viterbi decoder., , and . FCCM, page 60-69. IEEE, (1996)Exploring pipe implementations using an OpenCL framework for FPGAs., and . FPT, page 112-119. IEEE, (2015)A high-performance architecture for training Viola-Jones object detectors., and . FPT, page 174-181. IEEE, (2012)Caffeinated FPGAs: FPGA framework For Convolutional Neural Networks., , , , , and . FPT, page 265-268. IEEE, (2016)An efficient FPGA implementation of QR decomposition using a novel systolic array architecture based on enhanced vectoring CORDIC., , and . FPT, page 123-130. IEEE, (2014)Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding., , and . Inf. Process. Manag., 30 (6): 805-816 (1994)Optimization of data prefetch helper threads with path-expression based statistical modeling., and . ICS, page 210-221. ACM, (2007)