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A 1GHz ADPLL with a 1.25ps minimum-resolution sub-exponent TDC in 0.18µm CMOS., , , , and . ISSCC, page 482-483. IEEE, (2010)A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking., , , , , , , , , and 29 other author(s). IEEE J. Solid State Circuits, 54 (1): 197-209 (2019)A 5 Gb/s Transmitter With a TDR-Based Self-Calibration of Preemphasis Strength., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 57-II (5): 379-383 (2010)A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate., , , , , and . ISSCC, page 184-185. IEEE, (2009)A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking., , , , , , , , , and 39 other author(s). ISSCC, page 204-206. IEEE, (2018)A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-µm CMOS., , , , and . IEEE J. Solid State Circuits, 48 (2): 516-526 (2013)A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 μ m CMOS., , , and . IEEE J. Solid State Circuits, 45 (12): 2874-2881 (2010)A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18-μm CMOS., , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (2): 70-74 (2011)A 250-µW 2.4-GHz Fast-Lock Fractional-N Frequency Generation for Ultralow-Power Applications., , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (2): 106-110 (2017)A Distortion-Free General Purpose LVDS Driver., , , and . IEICE Trans. Electron., 92-C (2): 278-280 (2009)