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26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS., , , , , , and . ISSCC, page 436-437. IEEE, (2016)6.7 A 1.2e- temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA., , , , , , , , and . ISSCC, page 122-123. IEEE, (2016)19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC., , , , , and . ISSCC, page 336-337. IEEE, (2016)Balanced 3-phase analog signal processing for radio communications., , , , and . ISCAS, IEEE, (2006)A Fast fc Automatic Tuning Circuit with Wide Tuning Range for WCDMA Direct Conversion Receiver Systems., , , , and . IEICE Trans. Electron., 90-C (6): 1247-1252 (2007)A temperature-stable CMOS variable-gain amplifier with 80-dB linearly controlled gain range., , and . IEEE J. Solid State Circuits, 37 (5): 553-558 (2002)A Two-Gain-Stage Amplifier without an On-Chip Miller Capacitor in an LCD Driver IC., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 85-A (8): 1913-1920 (2002)A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique., , and . IEEE J. Solid State Circuits, 46 (6): 1360-1370 (2011)20 mV input, 4.2 V output SIDO boost converter with low-power controller and adaptive switch size selector for thermoelectric energy harvesting., , , and . A-SSCC, page 9-12. IEEE, (2016)A 7-bit 1.5-GS/s time-interleaved SAR ADC with dynamic track-and-hold amplifier., , , and . A-SSCC, page 293-296. IEEE, (2011)