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Run-time performance monitoring of hardware accelerators: POSTER., and . CF, page 289-291. ACM, (2019)Hardware design methodology using lightweight dataflow and its integration with low power techniques., , , , , , , , , and . J. Syst. Archit., (2017)Verification of Neural Networks: Challenges and Perspectives in the AIDOaRt Project (Short Paper)., , , , , and . IPS/RiCeRcA/SPIRIT@AI*IA, volume 3345 of CEUR Workshop Proceedings, CEUR-WS.org, (2022)Coarse grain reconfiguration: Power estimation and management flow for hybrid gated systems., and . ReConFig, page 1-4. IEEE, (2016)NeuPow: artificial neural networks for power and behavioral modeling of arithmetic components in 45nm ASICs technology., , , , , , and . CF, page 183-189. ACM, (2019)Power and clock gating modelling in coarse grained reconfigurable systems., , , , and . Conf. Computing Frontiers, page 384-391. ACM, (2016)Run-time Performance Monitoring of Heterogenous Hw/Sw Platforms Using PAPI., , , , , , , , and . CoRR, (2021)An integrated hardware/software design methodology for signal processing systems., , , , , , , , , and 1 other author(s). J. Syst. Archit., (2019)Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures., , , , and . J. Electr. Comput. Eng., (2016)Layering the monitoring action for improved flexibility and overhead control: work-in-progress., , , and . CoRR, (2021)