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Physical-design-friendly hierarchical logic built-in self-test - A case study., , , , , , , , , and 1 other author(s). ISQED, page 1-6. IEEE, (2012)Practical Challenges in Logic BIST Implementation., , , , , , , and . ATS, page 265. IEEE Computer Society, (2008)A Measurement Device for the Dynamic Unbalance of Crankshaft., , and . PACCS, page 285-288. IEEE Computer Society, (2009)Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains., , , , , , , , , and 2 other author(s). DFT, page 358-366. IEEE Computer Society, (2010)Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains., , , , , , , , , and 2 other author(s). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (3): 455-463 (2011)Logic BIST Architecture for System-Level Test and Diagnosis., , , , , , , , , and 5 other author(s). Asian Test Symposium, page 21-26. IEEE Computer Society, (2009)Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs., , , , , , , and . DFT, page 331-339. IEEE Computer Society, (2010)