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Benchmarking for research in power delivery networks of three-dimensional integrated circuits., , , , , , , , and . ISPD, page 17-24. ACM, (2013)Power delivery network design for wiring and TSV resource minimization in TSV-based 3-D ICs., , , , and . VLSI-DAT, page 1-4. IEEE, (2013)Selective body biasing for post-silicon tuning of sub-threshold designs: A semi-infinite programming approach with Incremental Hypercubic Sampling., , , , , , and . Integr., (2016)Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells., , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (12): 947-951 (2014)Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (11): 2097-2101 (2008)Incremental transient simulation of power grid., , , and . ISPD, page 93-100. ACM, (2014)Variation aware optimal threshold voltage computation for on-chip noise sensors., , , , , and . ICCAD, page 205-212. IEEE, (2014)Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM., , , , , , , and . Asian Test Symposium, page 123-127. IEEE Computer Society, (2013)On the Optimal Threshold Voltage Computation of On-Chip Noise Sensors., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (10): 1744-1754 (2016)Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (1): 146-155 (2017)