Author of the publication

b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS.

R. Inti, S. Shekhar, G. Balamurugan, J. Jaussi, C. Roberts, T. Hsueh, and B. Casper. VLSIC, page 346-. IEEE, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Sudip Roy

Sudip Kundu

Shekhar Priyadarshi

Sumit Shekhar

Hemabh Shekhar

Other publications of authors with the same name

A Dual-Polarization Silicon-Photonic Coherent Transmitter Supporting 552 Gb/s/wavelength.A. Ahmed, A. Elmoznine, D. Lim, Y. Ma, A. Rylyakov, and S. Shekhar. IEEE J. Solid State Circuits, 55 (9): 2597-2608 (2020)A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS.T. Musah, J. Jaussi, G. Balamurugan, S. Hyvonen, T. Hsueh, G. Keskin, S. Shekhar, J. Kennedy, S. Sen, R. Inti and 6 other author(s). IEEE J. Solid State Circuits, 49 (12): 3079-3090 (2014)Optimum Conditions for Efficient Second-Harmonic Power Generation in mm-Wave Harmonic Oscillators.A. Ghorbani-Nejad, A. Nikpaik, A. Nabavi, A. Shirazi, S. Mirabbasi, and S. Shekhar. IEEE J. Solid State Circuits, 57 (7): 2130-2142 (2022)A capacitor cross-coupled common-gate low-noise amplifier.W. Zhuo, X. Li, S. Shekhar, S. Embabi, J. de Gyvez, D. Allstot, and E. Sánchez-Sinencio. IEEE Trans. Circuits Syst. II Express Briefs, 52-II (12): 875-879 (2005)A Compact, Voltage-Mode Type-I PLL With Gain-Boosted Saturated PFD and Synchronous Peak Tracking Loop Filter.A. Sharkia, S. Aniruddhan, S. Mirabbasi, and S. Shekhar. IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (1): 43-53 (2019)Wideband CMOS Amplifier Design: Time-Domain Considerations.J. Walling, S. Shekhar, and D. Allstot. IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (7): 1781-1793 (2008)A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS.M. Mansuri, J. Jaussi, J. Kennedy, T. Hsueh, S. Shekhar, G. Balamurugan, F. O'Mahony, C. Roberts, R. Mooney, and B. Casper. IEEE J. Solid State Circuits, 48 (12): 3229-3242 (2013)A Type-I Sub-Sampling PLL With a 100×100 µm2 Footprint and -255-dB FOM.A. Sharkia, S. Mirabbasi, and S. Shekhar. IEEE J. Solid State Circuits, 53 (12): 3553-3564 (2018)Analog interference cancellation for full-duplex broadband power line communications.G. Prasad, L. Lampe, and S. Shekhar. ISPLC, page 1-6. IEEE, (2017)U-shaped slow-wave transmission lines in 0.18μm CMOS.H. Hsu, K. Dasgupta, N. Neihart, S. Shekhar, J. Walling, and D. Allstot. ISCAS, page 1296-1299. IEEE, (2010)

BibSonomy

Disambiguation of "Shekhar, Sudip"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS.

Please choose a person to relate this publication to

Sudip Roy

Sudip Kundu

Shekhar Priyadarshi

Sumit Shekhar

Hemabh Shekhar

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Shekhar, Sudip"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS.

Please choose a person to relate this publication to

Sudip Roy

Sudip Kundu

Shekhar Priyadarshi

Sumit Shekhar

Hemabh Shekhar

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS.