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Disambiguation of "Hsueh, Tzu-Chien"

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A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS.

, , , , , , and . VLSIC, page 346-. IEEE, (2015)

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Ching-Wen Hsueh

Yi-Ching Hsueh

Chieh Chien

Leo Fong-Ziang Hsueh

Rey-Djin Chien

 

Other publications of authors with the same name

A 1.2-5Gb/s 1.4-2pJ/b serial link in 22nm CMOS with a direct data-sequencing blind oversampling CDR., , , , and . VLSIC, page 350-. IEEE, (2015)A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS., , , , , , , , , and . ISSCC, page 402-403. IEEE, (2013)An on-die all-digital power supply noise analyzer with enhanced spectrum measurements., , , and . ESSCIRC, page 251-254. IEEE, (2014)A 3×3.8Gb/s four-wire high speed I/O link based on CDMA-like crosstalk cancellation., , and . CICC, page 121-124. IEEE, (2009)Random Sampling-and-Averaging Techniques for Single-Photon Arrival-Time Detections in Quantum Applications: Theoretical Analysis and Realization Methodology., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (4): 1452-1465 (2022)A 16 Gb/s four-wire CDMA-based high speed I/O link with transmitter timing adjustment., and . CICC, page 1-4. IEEE, (2010)A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 48 (12): 3229-3242 (2013)A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 49 (12): 3079-3090 (2014)Monolithic Silicon-Photonics Linear-Algebra Accelerators Enabling Next-Gen Massive MIMO., , and . CoRR, (2024)26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS., , , , , , , , , and 6 other author(s). ISSCC, page 440-441. IEEE, (2014)