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Reconfiguration Control Networks for TMR Systems with Module-Based Recovery.

, , , , , , and . FCCM, page 88-91. IEEE Computer Society, (2016)

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High-level synthesis of triple modular redundant FPGA circuits with energy efficient error recovery mechanisms.. University of New South Wales, Sydney, Australia, (2019)base-search.net (ftunswworks:oai:unsworks.library.unsw.edu.au:1959.4/62999).Single Event Effects Assessment of UltraScale+ MPSoC Systems under Atmospheric Radiation., , , , , , , , , and 2 other author(s). CoRR, (2023)The Impact of Hardware Folding on Dependability in Spaceborne FPGA-based Neural Networks., , , , , , and . FPT, page 1. IEEE, (2022)A soft error vulnerability analysis framework for Xilinx FPGAs., , and . FPGA, page 237-240. ACM, (2014)Dynamic scheduling of voter checks in FPGA-based TMR systems., , , and . FPT, page 169-172. IEEE, (2016)Detecting Hardware Faults in Approximate Adders via Minimum Redundancy., , and . IOLTS, page 1-7. IEEE, (2023)From C to Fault-Tolerant FPGA-Based Systems., , , , and . FCCM, page 212. IEEE Computer Society, (2018)FMER: A hybrid configuration memory error recovery scheme for highly reliable FPGA SoCs., , and . FPL, page 1-4. IEEE, (2016)Fine-Grained Module-Based Error Recovery in FPGA-Based TMR Systems., , , , , and . ACM Trans. Reconfigurable Technol. Syst., 11 (1): 4:1-4:23 (2018)FMER: An Energy-Efficient Error Recovery Methodology for SRAM-Based FPGA Designs., , and . IEEE Trans. Aerosp. Electron. Syst., 54 (6): 2695-2712 (2018)