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RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage., , , and . J. Electron. Test., 18 (2): 179-187 (2002)On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level., , , , , and . J. Electron. Test., 20 (4): 345-355 (2004)Investigating the Use of BICS to detect resistive-open defects in SRAMs., , , , , , and . IOLTS, page 200-201. IEEE Computer Society, (2010)Aging-Aware Power or Frequency Tuning With Predictive Fault Detection., , , , , , , , and . IEEE Des. Test Comput., 29 (5): 27-36 (2012)Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits., , , , , and . DDECS, page 34-37. IEEE Computer Society, (2008)Predictive error detection by on-line aging monitoring., , , , , , , and . IOLTS, page 9-14. IEEE Computer Society, (2010)MOSYS A Methodology for Automatic Object Identification from System Specification., , , , and . ISORC, page 198-201. IEEE Computer Society, (2000)Automatic Configuration of a Medical Imaging System to Unknown Delays in Synchronous Input Data Channels., , , , , , , , and . ISCAS, page 1185-1188. IEEE, (2010)Performance Sensor for Reliable Operation., , , , and . HCI (8), volume 10908 of Lecture Notes in Computer Science, page 347-365. Springer, (2018)Time Management for Low-Power Design of Digital Systems., , , , , , and . J. Low Power Electron., 4 (3): 410-419 (2008)