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Logic testing with test-per-clock pattern loading and improved diagnostic abilities.

, and . DDECS, page 54-59. IEEE, (2017)

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COMPAS - Compressed Test Pattern Sequencer for Scan Based Circuits., , and . EDCC, volume 3463 of Lecture Notes in Computer Science, page 403-414. Springer, (2005)On reliability enhancement using adaptive core voltage scaling and variations on nanoscale FPGAs., , , and . LATW, page 1-4. IEEE, (2014)Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor., , , , , and . J. Electron. Test., 20 (1): 109-122 (2004)A new method for in situ measurement of parameters and degradation processes in modern nanoscale programmable devices., and . Microprocess. Microsystems, 38 (6): 605-619 (2014)Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead., , , , and . DFT, page 300-308. IEEE Computer Society, (2006)On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faults., and . FPL, page 743-746. IEEE, (2012)Test response compaction method with improved detection and diagnostic abilities., and . Microelectron. Reliab., (2018)Design and optimisation of NiTi pressure gauge., and . DDECS, page 1-3. IEEE, (2017)Logic testing with test-per-clock pattern loading and improved diagnostic abilities., and . DDECS, page 54-59. IEEE, (2017)On measurement of parameters of programmable microelectronic nanostructures under accelerating extreme conditions (Xilinx 28nm XC7Z020 Zynq FPGA)., and . FPL, page 1-4. IEEE, (2013)