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System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 8 (2): 129-137 (2000)

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Hardware-Based Profiling: An Effective Technique for Profile-Driven Optimization., , , and . Int. J. Parallel Program., 24 (2): 187-206 (1996)Optimization of Instruction Fetch Mechanisms for High Issue Rates., , , and . ISCA, page 333-344. ACM, (1995)System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design., , , and . IEEE Trans. Very Large Scale Integr. Syst., 8 (2): 129-137 (2000)A Fast Interrupt Handling Scheme for VLIW Processors., , , , , and . IEEE PACT, page 136-141. IEEE Computer Society, (1998)Path Prediction for High Issue-Rate Processors., , and . IEEE PACT, page 178-188. IEEE Computer Society, (1997)Wavefront Scheduling: Path based Data Representation and Scheduling of Subgraphs., , and . MICRO, page 262-271. ACM/IEEE Computer Society, (1999)Accurate and Practical Profile-driven Compilation Using the Profile Buffer., , and . MICRO, page 36-45. ACM/IEEE Computer Society, (1996)Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings., , , , and . MICRO, page 201-211. ACM/IEEE Computer Society, (1996)Wavefront Scheduling: Path Based Data Representation and Scheduling of Subgraphs., , and . J. Instruction-Level Parallelism, (2000)A technique to determine power-efficient, high-performance superscalar processors., , and . HICSS (1), page 324-333. IEEE Computer Society, (1995)