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The Brain on Low Power Architectures - Efficient Simulation of Cortical Slow Waves and Asynchronous States., , , , , , , , , and 3 other author(s). CoRR, (2018)Real-time cortical simulations: energy and interconnect scaling on distributed systems., , , , , , , , , and 4 other author(s). CoRR, (2018)A hierarchical watchdog mechanism for systemic fault awareness on distributed systems., , , , , , , , , and . Future Gener. Comput. Syst., (2015)The Next Generation of Exascale-Class Systems: The ExaNeSt Project., , , , , , , , , and 8 other author(s). DSD, page 510-515. IEEE Computer Society, (2017)Large Scale Low Power Computing System - Status of Network Design in ExaNeSt and EuroExa Projects., , , , , , , , , and 3 other author(s). PARCO, volume 32 of Advances in Parallel Computing, page 750-759. IOS Press, (2017)Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms., , , , , , , , , and 11 other author(s). J. Syst. Archit., (2016)APENet: a high speed, low latency 3D interconnect network., , , , , , , and . CLUSTER, page 481. IEEE Computer Society, (2004)Distributed simulation of polychronous and plastic spiking neural networks: strong and weak scaling of a representative mini-application benchmark executed on a small-scale commodity cluster., , , , , , , , , and . CoRR, (2013)Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface., , , , , , , , , and . ReConFig, page 1-6. IEEE, (2013)ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces., , , , , , , , , and 2 other author(s). Future Gener. Comput. Syst., (2015)