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Performance-driven interconnection optimization for microarchitecture synthesis.

, , , and . EURO-DAC, page 118-123. IEEE Computer Society Press, (1992)

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A Hybrid Power Model for RTL Power Estimation., , , , and . ASP-DAC, page 551-556. IEEE, (1998)Estimation for maximum instantaneous current through supply lines for CMOS circuits., , and . IEEE Trans. Very Large Scale Integr. Syst., 8 (1): 61-73 (2000)A method of batching conflict routings in shuffle-exchange networks., , , and . Theor. Comput. Sci., (2014)Congestion and Timing Aware Macro Placement Using Machine Learning Predictions from Different Data Sources: Cross-design Model Applicability and the Discerning Ensemble., , , , , , , and . ISPD, page 195-202. ACM, (2022)Delay testing considering power supply noise effects., , and . ITC, page 181-190. IEEE Computer Society, (1999)Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices., and . DAC, page 760-765. ACM Press, (1999)Performance-driven interconnection optimization for microarchitecture synthesis., , , and . EURO-DAC, page 118-123. IEEE Computer Society Press, (1992)Estimation of maximum power supply noise for deep sub-micron designs., , and . ISLPED, page 233-238. ACM, (1998)Delay testing considering crosstalk-induced effects., , , and . ITC, page 558-567. IEEE Computer Society, (2001)HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis., , and . ISQED, page 307-312. IEEE Computer Society, (2001)