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Width minimization in the Single-Electron Transistor array synthesis.

C. Liu, C. Chiang, C. Huang, C. Wang, Y. Chen, S. Datta, and V. Narayanan. DATE, page 1-4. European Design and Automation Association, (2014)

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Yao Wang

Wang Yao

Chun Wang

Other publications of authors with the same name

A register-transfer level testability analyzer.Y. Chen, C. Wang, C. Huang, and H. Lin. SoCC, page 219-224. IEEE, (2011)Low-Latency Service Chaining With Predefined NSH-Based Multipath Across Multiple Datacenters.Y. Wang, R. Hwang, and Y. Lin. IEEE Trans. Netw. Serv. Manag., 19 (4): 4721-4733 (December 2022)Verification of Pin-Accurate Port Connections.G. Lee, J. Huang, C. Wang, and J. Jou. IEEE Des. Test Comput., 25 (5): 478-486 (2008)IMU-based Smart Knee Pad for Walking Distance and Stride Count Measurement.T. Wang, Y. Chang, C. Chen, Y. Lee, C. Lin, Y. Chen, and C. Wang. ISQED, page 173-178. IEEE, (2020)An Efficient Interpolation-Based Projected Sum of Product Decomposition via Genetic Algorithm.T. Chen, C. Wang, C. Huang, and Y. Chen. J. Multiple Valued Log. Soft Comput., 27 (1): 1-19 (2016)Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays.Y. Li, C. Huang, C. Wu, Y. Chen, C. Wang, S. Datta, and V. Narayanan. IEEE Trans. Very Large Scale Integr. Syst., 25 (4): 1477-1489 (2017)LOOPLock 2.0: An Enhanced Cyclic Logic Locking Approach.X. Yang, P. Chen, H. Chiang, C. Lin, Y. Chen, and C. Wang. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (1): 29-34 (2022)Error Injection & Correction: An efficient formal logic restructuring algorithm.C. Huang, D. Lee, C. Lin, and C. Wang. ISOCC, page 188-191. IEEE, (2012)High level equivalence symmetric input identification.M. Su, and C. Wang. ASP-DAC, page 249-253. IEEE, (2006)On reconfigurable single-electron transistor arrays synthesis using reordering techniques.C. Chiang, L. Tang, C. Wang, C. Huang, Y. Chen, S. Datta, and V. Narayanan. DATE, page 1807-1812. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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Disambiguation of "Wang, Chun-Yao"

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Width minimization in the Single-Electron Transistor array synthesis.

Please choose a person to relate this publication to

Yao Wang

Wang Yao

Chun Wang

Chun Wang

Chun Wang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wang, Chun-Yao"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Width minimization in the Single-Electron Transistor array synthesis.

Please choose a person to relate this publication to

Yao Wang

Wang Yao

Chun Wang

Chun Wang

Chun Wang

Other publications of authors with the same name

Disambiguation

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URL
DOI
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Chicago
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Width minimization in the Single-Electron Transistor array synthesis.