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Disambiguation of "Amemiya, Yoshihito"

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A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs.

, , , and . ASP-DAC, page 95-96. IEEE, (2009)

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Yoshihito Ogasawara

Hiroshi Amemiya

Yoshihito Ogasawara

Yoshihito Muroji

Yoshihito Ogasawara

 

Other publications of authors with the same name

Basic Circuit Design of a Neural Processor: Analog CMOS Implementation of Spiking Neurons and Dynamic Synapses., , and . J. Robotics Mechatronics, 15 (2): 208-218 (2003)CMOS Smart Sensor for Monitoring the Quality of Perishables., , , and . IEEE J. Solid State Circuits, 42 (4): 798-803 (2007)An all-analog expandable neural network LSI with on-chip backpropagation learning., and . IEEE J. Solid State Circuits, 29 (9): 1086-1093 (September 1994)A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters., , , , and . Neurocomputing, 71 (1-3): 3-12 (2007)An analog CMOS chip implementing a CNN-based locomotion controller for quadruped walking robots., , and . ISCAS (3), page 1-4. IEEE, (2004)A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs., , , and . ASP-DAC, page 95-96. IEEE, (2009)A 0.6-4.5 GHz inductorless CMOS low noise amplifier with gyrator-C network., , , , and . ICECS, page 326-329. IEEE, (2011)Noise-Tolerant Analog Circuits for Sensory Segmentation Based on Symmetric STDP Learning., , and . ICONIP (2), volume 5507 of Lecture Notes in Computer Science, page 851-858. Springer, (2008)An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs., , , , and . IEICE Trans. Electron., 93-C (6): 835-841 (2010)High-Resistance Resistor Consisting of a Subthreshold CMOS Differential Pair., , , and . IEICE Trans. Electron., 93-C (6): 741-746 (2010)