Author of the publication

A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS.

, , , , , , , , , and . IEEE J. Solid State Circuits, 52 (4): 940-949 (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Power-aware global signaling strategies., , , , , and . ISCAS (1), page 604-607. IEEE, (2005)Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses., , , and . ISLPED, page 194-199. ACM, (2004)A novel buffer circuit for energy efficient signaling in dual-VDD systems., and . ACM Great Lakes Symposium on VLSI, page 462-467. ACM, (2005)Active shielding of RLC global interconnects., , and . Timing Issues in the Specification and Synthesis of Digital Systems, page 98-104. ACM, (2002)High-Performance On-Chip Interconnect Circuit Technologies for sub-65nm CMOS.. SoCC, page 324. IEEE, (2005)DVS for On-Chip Bus Designs Based on Timing Error Correction, , , , and . CoRR, (2007)A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS., , , , , , , and . ISSCC, page 182-184. IEEE, (2012)DVS for On-Chip Bus Designs Based on Timing Error Correction., , , , and . DATE, page 80-85. IEEE Computer Society, (2005)A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition., , , , , , , , , and 2 other author(s). VLSI Circuits, page 234-. IEEE, (2019)A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS., , , , , , , , , and 1 other author(s). VLSI Circuits, page 50-. IEEE, (2019)