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An FPGA-based 4K UHDTV H.264/AVC video decoder.

, , and . ICME Workshops, page 1-4. IEEE Computer Society, (2013)

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Transform-based fast mode and depth decision algorithm for HEVC intra prediction., , and . ASICON, page 1-4. IEEE, (2013)A Frame-Parallel 2 Gpixel/s Video Decoder Chip for UHDTV and 3-DTV/FTV Applications., , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (12): 2768-2781 (2015)Intra prediction architecture for H.264/AVC QFHD encoder., , , and . PCS, page 450-453. IEEE, (2010)Embedded Frame Compression for Energy-Efficient Computer Vision Systems., , , and . ISCAS, page 1-5. IEEE, (2018)A fixed-complexity HEVC inter mode filtering algorithm based on distribution of IME-FME cost ratio., , , and . ISCAS, page 617-620. IEEE, (2015)A 610 Mbin/s CABAC decoder for H.265/HEVC level 6.1 applications., , , and . ICIP, page 1268-1272. IEEE, (2014)A high-performance CABAC encoder architecture for HEVC and H.264/AVC., , , and . ICIP, page 1568-1572. IEEE, (2013)An Advanced Hierarchical Motion Estimation Scheme With Lossless Frame Recompression and Early-Level Termination for Beyond High-Definition Video Coding., , , and . IEEE Trans. Multim., 14 (2): 237-249 (2012)Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA., , , and . ASP-DAC, page 184-189. IEEE, (2018)High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for Ultra-HD HEVC Video Encoding., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (12): 3138-3142 (2015)