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Digital LDO with Time-Interleaved Comparators for Fast Response and Low Ripple.

, , , and . ISVLSI, page 337-342. IEEE Computer Society, (2016)

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Cache Design with Domain Wall Memory., , , , , , and . IEEE Trans. Computers, 65 (4): 1010-1024 (2016)Proposal For Neuromorphic Hardware Using Spin Devices, , , and . CoRR, (2012)Design and Synthesis of Ultra Low Energy Spin-Memristor Threshold Logic., , and . CoRR, (2014)Spin Neurons: A Possible Path to Energy-Efficient Neuromorphic Computers., , and . CoRR, (2013)Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing., , , and . IEEE Trans. Neural Networks Learn. Syst., 27 (9): 1907-1919 (2016)Low Power Implantable Spike Sorting Scheme Based on Neuromorphic Classifier with Supervised Training Engine., , , , and . ISVLSI, page 266-271. IEEE Computer Society, (2017)Energy efficient computing using coupled Dual-Pillar Spin Torque Nano Oscillators., , and . NANOARCH, page 28-29. IEEE Computer Society, (2013)Ultra-low Energy, High Performance and Programmable Magnetic Threshold Logic., , and . CoRR, (2013)Power-efficient Spike Sorting Scheme Using Analog Spiking Neural Network Classifier., , , , and . ACM J. Emerg. Technol. Comput. Syst., 17 (2): 12:1-12:29 (2021)Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage., , , and . ACM J. Emerg. Technol. Comput. Syst., 12 (1): 4:1-4:27 (2015)