( en | de | ru )

 

Disambiguation of "Valero, Mateo"

Author of the publication

copydeleteadd this publication to your clipboard
Reducing Cache Coherence Traffic with Hierarchical Directory Cache and NUMA-Aware Runtime Scheduling.

, , , , , , , and . PACT, page 275-286. ACM, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ana Maria Mateo Rosell

Carlos Mateo Balmelli

Mateo Hermel

Alejandro Valero

Silvia Valero

 

Other publications of authors with the same name

Automatic generation of loop scheduling for VLIW., , , and . PACT, page 306-309. IFIP Working Group on Algol / ACM, (1995)Partitioning: An Essential Step in Mapping Algorithms Into Systolic Array Processors., , and . Computer, 20 (7): 77-89 (1987)Register Constrained Modulo Scheduling., , , and . IEEE Trans. Parallel Distributed Syst., 15 (5): 417-430 (2004)Errata on "Measuring Experimental Error in Microprocessor Simulation"., , , , , , and . SIGARCH Comput. Archit. News, 30 (1): 2-4 (2002)CPU Accounting in CMP Processors., , , , , and . IEEE Comput. Archit. Lett., 8 (1): 17-20 (2009)Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications., , , , , , , , , and 14 other author(s). ACM Trans. Archit. Code Optim., 20 (2): 28:1-28:25 (June 2023)Profile-guided transaction coalescing - lowering transactional overheads by merging transactions., , , , and . ACM Trans. Archit. Code Optim., 10 (4): 50:1-50:18 (2013)Hardware transactional memory with software-defined conflicts., , , , , , , and . ACM Trans. Archit. Code Optim., 8 (4): 31:1-31:20 (2012)The International Exascale Software Project roadmap., , , , , , , , , and 55 other author(s). Int. J. High Perform. Comput. Appl., 25 (1): 3-60 (2011)A latency-conscious SMT branch prediction architecture., , , and . Int. J. High Perform. Comput. Netw., 2 (1): 11-21 (2004)