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FPGA-Based Variable Length Decoders., , , and . VLSI-SOC, page 437-441. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)Software Metrics and Microcode: A Case Study., , and . Journal of Software Maintenance, 8 (3): 199-224 (1996)Reconfigurable repetitive padding unit., and . ACM Great Lakes Symposium on VLSI, page 98-103. ACM, (2002)A Fuzzy Reasoning Database Question Answering System., , and . IEEE Trans. Knowl. Data Eng., 6 (6): 868-882 (1994)High-Performance 3-1 Interlock Collapsing ALU's., and . IEEE Trans. Computers, 43 (3): 257-268 (1994)Interlock Collapsing ALU's., , and . IEEE Trans. Computers, 42 (7): 825-839 (1993)Hard-Wired Multipliers with Encoded Partial Products., , and . IEEE Trans. Computers, 40 (11): 1181-1197 (1991)Correction: IEEE Transactions on Computers 42(1): 127 (1993).Hardwired Paeth Codec for Portable Network Graphics (PNG)., and . EUROMICRO, page 2318-2325. IEEE Computer Society, (1999)A Low-Power Multithreaded Processor for Software Defined Radio., , , , , and . VLSI Signal Processing, 43 (2-3): 143-159 (2006)Systematic Customization of On-Chip Crossbar Interconnects., , , and . ARC, volume 4419 of Lecture Notes in Computer Science, page 61-72. Springer, (2007)