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Scalable Hardware Memory Disambiguation for High-ILP Processors., , , , and . IEEE Micro, 24 (6): 118-127 (2004)Designing a Modern Memory Hierarchy with Hardware Prefetching., , and . IEEE Trans. Computers, 50 (11): 1202-1218 (2001)Static energy reduction techniques for microprocessor caches., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (3): 303-313 (2003)Neural Acceleration for General-Purpose Approximate Programs., , , and . IEEE Micro, 33 (3): 16-27 (2013)The SimpleScalar tool set, version 2.0., and . SIGARCH Comput. Archit. News, 25 (3): 13-25 (1997)Architectural versus physical solutions for on-chip communication challenges.. CODES+ISSS, page 74. ACM, (2003)Neural Acceleration for General-Purpose Approximate Programs., , , and . MICRO, page 449-460. IEEE Computer Society, (2012)Low-power, high-performance analog neural branch prediction., , and . MICRO, page 447-458. IEEE Computer Society, (2008)Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency., , , and . MICRO, page 222-233. IEEE Computer Society, (2008)Universal Mechanisms for Data-Parallel Architectures., , , and . MICRO, page 303-314. IEEE Computer Society, (2003)