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Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks.

, , , and . IET Comput. Digit. Tech., 5 (1): 1-15 (2011)

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MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm., , and . ICCAD, page 678-684. IEEE Computer Society, (2008)Improving GA-Based NoC Mapping Algorithms Using a Formal Model., , and . ISVLSI, page 344-349. IEEE Computer Society, (2014)CoRaS: A multiprocessor key corruption and random round swapping for power analysis side channel attacks: A DES case study., , and . ISCAS, page 253-256. IEEE, (2012)A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES., , , and . ISVLSI, page 76-83. IEEE Computer Socity, (2013)Efficient implementation of multi-moduli architectures for Binary-to-RNS conversion., , and . ASP-DAC, page 819-824. IEEE, (2012)DARNS: A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks., , and . ASP-DAC, page 620-625. IEEE, (2013)RIJID: Random Code Injection to Mask Power Analysis based Side Channel Attacks., , and . DAC, page 489-492. IEEE, (2007)RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors., , , and . DIPES/BICC, volume 329 of IFIP Advances in Information and Communication Technology, page 137-144. Springer, (2010)A smart random code injection to mask power analysis based side channel attacks., , and . CODES+ISSS, page 51-56. ACM, (2007)DRMA: dynamically reconfigurable MPSoC architecture., , , , , , and . ACM Great Lakes Symposium on VLSI, page 239-244. ACM, (2013)