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Designing Efficient Heterogeneous Memory Architectures., , , , , and . IEEE Micro, 35 (4): 60-68 (2015)Many-Core vs. Many-Thread Machines: Stay Away From the Valley., , , , , and . IEEE Comput. Archit. Lett., 8 (1): 25-28 (2009)HMG: Extending Cache Coherence Protocols Across Modern Hierarchical Multi-GPU Systems., , , , , and . HPCA, page 582-595. IEEE, (2020)Routing table minimization for irregular mesh NoCs., , , and . DATE, page 942-947. EDA Consortium, San Jose, CA, USA, (2007)The Architectural Implications of Distributed Reinforcement Learning on CPU-GPU Systems., , , , , , and . CoRR, (2020)Application-aware Memory System for Fair and Efficient Execution of Concurrent GPGPU Applications., , , , , , and . GPGPU@ASPLOS, page 1. ACM, (2014)The Power of Priority: NoC Based Distributed Cache Coherency., , , , and . NOCS, page 117-126. IEEE Computer Society, (2007)Beyond the socket: NUMA-aware GPUs., , , , , , , and . MICRO, page 123-135. ACM, (2017)Scaling the Power Wall: A Path to Exascale., , , , , , , , , and 2 other author(s). SC, page 830-841. IEEE Computer Society, (2014)Toggle-Aware Compression for GPUs., , , , , and . IEEE Comput. Archit. Lett., 14 (2): 164-168 (2015)