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Disambiguation of "Seong, Taeho"

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A Low-Jitter and Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Real-Time PVT Calibrator With Replica-Delay Cells.

, , , and . IEEE J. Solid State Circuits, 51 (2): 401-411 (2016)

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Ki-Chang Seong

Seunghyeon Seong

Nak-Hyon Seong

Hong-Jae Seong

Seong Lee

 

Other publications of authors with the same name

A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier With a Two-Phase PVT-Calibrator for ΔΣ PLLs., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (3): 635-644 (2015)A 12.8-15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation., , , , , and . IEEE J. Solid State Circuits, 59 (2): 424-434 (February 2024)Analysis and Design of a Core-Size-Scalable Low Phase Noise LC-VCO for Multi-Standard Cellular Transceivers., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (3): 781-790 (2015)Ultralow In-Band Phase Noise Injection-Locked Frequency Multiplier Design Based on Open-Loop Frequency Calibration., , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (9): 701-705 (2014)A -242dB FOM and -75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC., , , and . ISSCC, page 396-398. IEEE, (2018)A 320-fs RMS Jitter and - 75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC., , , and . IEEE J. Solid State Circuits, 54 (9): 2501-2512 (2019)A Low-Jitter and Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Real-Time PVT Calibrator With Replica-Delay Cells., , , and . IEEE J. Solid State Circuits, 51 (2): 401-411 (2016)An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators., , , , , , , and . IEEE J. Solid State Circuits, 54 (12): 3466-3477 (2019)A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping Δ ΣM., , , , and . ISSCC, page 442-444. IEEE, (2021)A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator., , , , , and . IEEE J. Solid State Circuits, 56 (1): 298-309 (2021)