( en | de | ru )

 

Disambiguation of "Li, Hai Helen"

Author of the publication

copydeleteadd this publication to your clipboard
A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks.

, , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (8): 1353-1366 (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Hai Li

Hai Li

Hai-Quing Li

Aili Helenius

Anttiheikki Helenius

 

Other publications of authors with the same name

Memristor-based synapse design and a case study in reconfigurable systems., , , , and . IJCNN, page 1-6. IEEE, (2013)Accelerating graph computation with racetrack memory and pointer-assisted graph representation., , , and . DATE, page 1-4. European Design and Automation Association, (2014)ReSiPE: ReRAM-based Single-Spiking Processing-In-Memory Engine., , and . DAC, page 1-6. IEEE, (2020)Neuromorphic acceleration for context aware text image recognition., , , , and . SiPS, page 268-273. IEEE, (2014)Build reliable and efficient neuromorphic design with memristor technology., , , and . ASP-DAC, page 224-229. ACM, (2019)SiDA: Sparsity-Inspired Data-Aware Serving for Efficient and Scalable Large Mixture-of-Experts Models., , , , , , , , , and . CoRR, (2023)Array Organization and Data Management Exploration in Racetrack Memory., , , , and . IEEE Trans. Computers, 65 (4): 1041-1054 (2016)SIO: Synthetic In-Distribution Data Benefits Out-of-Distribution Detection., , , , , and . CoRR, (2023)FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (7): 1167-1180 (2017)A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (8): 1353-1366 (2017)