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Disambiguation of "Devadas, Srinivas"

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A Methodology for Accurate Performance Evaluation in Architecture Exploration.

, , and . DAC, page 927-932. ACM Press, (1999)

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Vinay Devadas

Deepika Devadas

Srinivas Jagarlamudi

Srinivas Yarlanki

Girish Srinivas

 

Other publications of authors with the same name

Topological Optimization of Multiple-Level Array Logic., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 6 (6): 915-941 (1987)Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures., , and . Des. Autom. Embed. Syst., 4 (1): 5-22 (1999)Code density optimization for embedded DSP processors using data compression techniques., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (7): 601-608 (1998)A unified approach to the synthesis of fully testable sequential machines., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (1): 39-50 (1991)Irredundant sequential machines via optimal logic synthesis., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (1): 8-18 (1990)Addendum to "Synthesis of robust delay-fault testable circuits: Theory"., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (4): 445-446 (1996)Logic verification algorithms and their parallel implementation., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 8 (2): 181-189 (1989)Verification of relations between synchronous machines., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (12): 1947-1959 (1993)Robust and Reverse-Engineering Resilient PUF Authentication and Key-Exchange by Substring Matching., , , , and . IEEE Trans. Emerg. Top. Comput., 2 (1): 37-49 (2014)MI6: Secure Enclaves in a Speculative Out-of-Order Processor., , , , , and . CoRR, (2018)