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A binding algorithm in high-level synthesis for path delay testability.

. ASP-DAC, page 546-551. IEEE, (2013)

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Hybrid test application in hybrid delay scan design., , , and . European Test Symposium, page 247. IEEE Computer Society, (2010)False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults., , and . ATS, page 65-68. IEEE, (2007)An FPGA-based fail-soft system with adaptive reconfiguration., , , , and . IOLTS, page 127-132. IEEE Computer Society, (2010)A study of thermal sensation with visuo-thermal projection interfaces., , and . GCCE, page 118-119. IEEE, (2013)A Practical Approach to Threshold Test Generation for Error Tolerant Circuits., , , and . Asian Test Symposium, page 171-176. IEEE Computer Society, (2009)A binding algorithm in high-level synthesis for path delay testability.. ASP-DAC, page 546-551. IEEE, (2013)Design for Testability Based on Single-Port-Change Delay Testing for Data Paths., , , and . Asian Test Symposium, page 254-259. IEEE Computer Society, (2005)A Fast Threshold Test Generation Algorithm Based on 5-Valued Logic., , , and . DELTA, page 345-349. IEEE Computer Society, (2010)A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification., , , and . VTS, page 71-76. IEEE Computer Society, (2009)Fast false path identification based on functional unsensitizability using RTL information., , , and . ASP-DAC, page 660-665. IEEE, (2009)