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O With DFE Receiver in 32 nm SOI CMOS Technology.

T. Dickson, Y. Liu, S. Rylov, A. Agrawal, S. Kim, P. Hsieh, J. Bulzacchelli, M. Ferriss, H. Ainspan, A. Rylyakov, B. Parker, M. Beakes, C. Baks, L. Shan, Y. Kwark, J. Tierno, and D. Friedman. IEEE J. Solid State Circuits, 50 (8): 1917-1931 (2015)

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Stanley Baksi

Rakesh Bakshi

Janis Baksa

Alexander Bakst

István Baksa

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Low-Power 16 x 10 Gb/s Bi-Directional Single Chip CMOS Optical Transceivers Operating at ≪ 5 mW/Gb/s/link.C. Schow, F. Doany, C. Chen, A. Rylyakov, C. Baks, D. Kuchta, R. John, and J. Kash. IEEE J. Solid State Circuits, 44 (1): 301-313 (2009)A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks.A. Rylyakov, J. Proesel, S. Rylov, B. Lee, J. Bulzacchelli, A. Ardey, B. Parker, M. Beakes, C. Baks, C. Schow and 1 other author(s). IEEE J. Solid State Circuits, 50 (12): 3120-3132 (2015)A WDM-Compatible 4 × 32-Gb/s CMOS-driven electro-absorption modulator array.B. Lee, R. Rimolo-Donadio, A. Rylyakov, J. Proesel, J. Bulzacchelli, C. Baks, M. Meghelli, C. Schow, A. Ramaswamy, J. Roth and 4 other author(s). OFC, page 1-3. IEEE, (2015)Antenna-in-package design and module integration for millimeter-wave communication and 5G.X. Gu, B. Sadhu, D. Liu, C. Baks, and A. Valdes-Garcia. VLSI-DAT, page 1-2. IEEE, (2018)30Gbps optical link utilizing heterogeneously integrated III-V/Si photonics and CMOS circuits.N. Dupuis, B. Lee, J. Proesel, A. Rylyakov, R. Rimolo-Donadio, C. Baks, C. Schow, A. Ramaswamy, J. Roth, R. Guzzon and 3 other author(s). OFC, page 1-3. IEEE, (2014)FEC-Free 60-Gb/s Silicon Photonic Link Using SiGe-Driver ICs Hybrid-Integrated with Photonics-Enabled CMOS.B. Lee, N. Dupuis, J. Orcutt, J. Ayala, K. Nummy, H. Ainspan, J. Proesel, C. Baks, D. Gill, M. Meghelli and 1 other author(s). OFC, page 1-3. IEEE, (2018)System-Level Demonstration of a Dynamically Reconfigured Burst-Mode Link Using a Nanosecond Si-Photonic Switch.A. Forencich, V. Kamchevska, N. Dupuis, B. Lee, C. Baks, G. Papen, and L. Schares. OFC, page 1-3. IEEE, (2018)A Nonblocking 4×4 Mach-Zehnder Switch with Integrated Gain and Nanosecond-Scale Reconfiguration Time.N. Dupuis, F. Doany, R. Budd, L. Schares, C. Baks, D. Kuchta, T. Hirokawa, and B. Lee. OFC, page 1-3. IEEE, (2019)A WDM 4×28Gbps integrated silicon photonic transmitter driven by 32nm CMOS driver ICs.A. Ramaswamy, J. Roth, E. Norberg, R. Guzzon, J. Shin, J. Imamura, B. Koch, D. Sparacin, G. Fish, B. Lee and 6 other author(s). OFC, page 1-3. IEEE, (2015)A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage.B. Sadhu, A. Valdes-Garcia, J. Plouchart, H. Ainspan, A. Gupta, M. Ferriss, M. Yeck, M. Sanduleanu, X. Gu, C. Baks and 2 other author(s). IEEE J. Solid State Circuits, 55 (6): 1516-1529 (2020)

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Disambiguation of "Baks, Christian W."

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A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.

Please choose a person to relate this publication to

Stanley Baksi

Rakesh Bakshi

Janis Baksa

Alexander Bakst

István Baksa

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Baks, Christian W."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.

Please choose a person to relate this publication to

Stanley Baksi

Rakesh Bakshi

Janis Baksa

Alexander Bakst

István Baksa

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.