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Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties.

J. Lee, N. Vijaykrishnan, and M. Irwin. IEEE Trans. Circuits Syst. Video Techn., 16 (5): 655-662 (2006)

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P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

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On the Detection of Clones in Sensor Networks Using Random Key Predistribution.R. Brooks, P. Govindaraju, M. Pirretti, N. Vijaykrishnan, and M. Kandemir. IEEE Trans. Syst. Man Cybern. Part C, 37 (6): 1246-1258 (2007)Harnessing ferroelectrics for non-volatile memories and logic.S. Gupta, D. Wang, S. George, A. Aziz, X. Li, S. Datta, and V. Narayanan. ISQED, page 29-34. IEEE, (2017)Noise Aware Power Adaptive Partitioned Deep Networks for Mobile Visual Assist Platforms.P. Zientara, J. Sampson, and V. Narayanan. SoCC, page 186-191. IEEE, (2018)Using complete system simulation to characterize SPECjvm98 benchmarks.T. Li, L. John, N. Vijaykrishnan, A. Sivasubramaniam, J. Sabarinathan, and A. Murthy. ICS, page 22-33. ACM, (2000)A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support.S. Srinivasa, A. Ramanathan, X. Li, W. Chen, F. Hsueh, C. Yang, C. Shen, J. Shieh, S. Gupta, M. Chang and 3 other author(s). ISLPED, page 34:1-34:6. ACM, (2018)X-VS: Crossbar-Based Processing-in-Memory Architecture for Video Summarization.N. Challapalle, M. Chandran, S. Rampalli, and V. Narayanan. ISVLSI, page 592-597. IEEE, (2020)Java Runtime Systems: Characterization and Architectural Implications.R. Radhakrishnan, N. Vijaykrishnan, L. John, A. Sivasubramaniam, J. Rubio, and J. Sabarinathan. IEEE Trans. Computers, 50 (2): 131-146 (2001)Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling.S. Yang, P. Gupta, M. Wolf, D. Serpanos, V. Narayanan, and Y. Xie. ACM Trans. Embed. Comput. Syst., 11 (3): 62:1-62:16 (2012)An Accuracy Tunable Non-Boolean Co-Processor Using Coupled Nano-Oscillators.N. Gala, S. Krithivasan, W. Tsai, X. Li, V. Narayanan, and V. Kamakoti. ACM J. Emerg. Technol. Comput. Syst., 14 (1): 1:1-1:28 (2018)Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications.K. Ma, X. Li, S. Li, Y. Liu, J. Sampson, Y. Xie, and V. Narayanan. IEEE Micro, 35 (5): 32-40 (2015)

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Disambiguation of "Vijaykrishnan, Narayanan"

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Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties.

Please choose a person to relate this publication to

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Vijaykrishnan, Narayanan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties.

Please choose a person to relate this publication to

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties.