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StageNet: A Reconfigurable Fabric for Constructing Dependable CMPs., , , and . IEEE Trans. Computers, 60 (1): 5-19 (2011)Tolerating First Level Memory Access Latency in High-Performance Systems., , and . ICPP (1), page 36-43. CRC Press, (1992)The Effect of Compiler Optimizations on Available Parallelism in Scalar Programs., , , , and . ICPP (2), page 142-145. CRC Press, (1991)Scratch That (But Cache This): A Hybrid Register Cache/Scratchpad for GPUs., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (11): 2779-2789 (2018)Increasing hardware efficiency with multifunction loop accelerators., , , and . CODES+ISSS, page 276-281. ACM, (2006)Embracing heterogeneity with dynamic core boosting., and . Conf. Computing Frontiers, page 10:1-10:10. ACM, (2014)Uncovering hidden loop level parallelism in sequential applications., , , and . HPCA, page 290-301. IEEE Computer Society, (2008)Gadara: Dynamic Deadlock Avoidance for Multithreaded Programs., , , , and . OSDI, page 281-294. USENIX Association, (2008)Cost-efficient soft error protection for embedded microprocessors., , , and . CASES, page 421-431. ACM, (2006)Scalable subgraph mapping for acyclic computation accelerators., , , and . CASES, page 147-157. ACM, (2006)