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Disambiguation of "Sakurai, Takayasu"

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Optimal design to maximize efficiency of single-inductor multiple-output buck converters in discontinuous conduction mode for IoT applications.

, , , , and . ICICDT, page 1-4. IEEE, (2015)

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Yoriko Sakurai

Kaneaki Sakurai

Takayasu Shimizu

Miriam Takayasu

 

Other publications of authors with the same name

On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (10): 1876-1880 (2012)Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering., and . IPSJ Trans. Syst. LSI Des. Methodol., (2009)Power distribution analysis of VLSI interconnects using model orderreduction., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (6): 739-745 (2002)High-Speed Searching of Optimum Switching Pattern for Digital Active Gate Drive to Adapt to Various Load Conditions., , , , , , , and . IEEE Trans. Ind. Electron., 69 (5): 5185-5194 (2022)Statistical leakage current reduction in high-leakage environments using locality of block activation in time domain., , and . IEEE J. Solid State Circuits, 39 (9): 1497-1503 (2004)A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current., , and . IEEE J. Solid State Circuits, 35 (10): 1498-1501 (2000)A 6.78-MHz Multiple-Transmitter Wireless Power Transfer System With Efficiency Maximization by Adaptive Magnetic Field Adder IC., , and . IEEE J. Solid State Circuits, 57 (8): 2390-2403 (2022)Reducing IR drop in 3D integration to less than 1/4 using Buck Converter on Top die (BCT) scheme., , , , , , , and . ISQED, page 210-215. IEEE, (2013)A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD., , , , , , and . ISSCC, page 238-239. IEEE, (2009)A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking., , , , , , , and . ISSCC, page 244-245. IEEE, (2009)