( en | de | ru )

 

Disambiguation of "Lo, Wei-Chung"

Author of the publication

copydeleteadd this publication to your clipboard
3D research activities in ITRI.

. 3DIC, page FS3.1. IEEE, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Wei-Chung Hsieh

Wei-chung Wang

Chung-Wei Lin

Wei-chung Chang

Wei-Chung Li

 

Other publications of authors with the same name

Performance and process characteristic of glass interposer with through-glass-via(TGV)., , , , , , , , , and 6 other author(s). 3DIC, page 1-7. IEEE, (2013)8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips., , , , , , , , , and 11 other author(s). IEEE Trans. Circuits Syst. II Express Briefs, 71 (4): 2304-2308 (April 2024)An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology., , , , , , , , , and 5 other author(s). VLSI Technology and Circuits, page 262-263. IEEE, (2022)A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips., , , , , , , , , and 15 other author(s). IEEE J. Solid State Circuits, 58 (3): 877-892 (March 2023)16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips., , , , , , , , , and 11 other author(s). ISSCC, page 250-252. IEEE, (2021)A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices., , , , , , , , , and 10 other author(s). ISSCC, page 1-3. IEEE, (2022)A 4K-400K Wide Operating-Temperature-Range MRAM Technology with Ultrathin Composite Free Layer and Magnesium Spacer., , , , , , , , , and 11 other author(s). VLSI Technology and Circuits, page 379-380. IEEE, (2022)A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration., , , , , , , , , and . A-SSCC, page 1-3. IEEE, (2021)A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 59 (1): 196-207 (January 2024)A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices., , , , , , , , , and 7 other author(s). ISSCC, page 126-127. IEEE, (2023)