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Disambiguation of "Bae, Seung-Jun"

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F5: Wireline transceivers for Mega Data Centers: 50Gb/s and beyond.

, , , , , and . ISSCC, page 512-514. IEEE, (2017)

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Jun-Sang Bae

Jung-Hun Seung

Soonil Bae

Jun Jun Lu

Han Bae

 

Other publications of authors with the same name

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion., , , , , , , , , and 14 other author(s). IEEE J. Solid State Circuits, 43 (1): 121-131 (2008)A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction., , , , , , , , , and 20 other author(s). IEEE J. Solid State Circuits, 46 (1): 107-118 (2011)An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques., , , , , , , , , and 18 other author(s). IEEE J. Solid State Circuits, 56 (1): 212-224 (2021)A VCDL-based 60-760-MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme., , , and . IEEE J. Solid State Circuits, 40 (5): 1119-1129 (2005)23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme., , , , , , , , , and 27 other author(s). ISSCC, page 390-391. IEEE, (2017)A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (10): 2495-2503 (2015)Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 53 (10): 2906-2916 (2018)A 0.13-µm CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN., , , , , , and . IEEE J. Solid State Circuits, 44 (11): 3146-3162 (2009)A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s., , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (1): 122-133 (2016)A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking., , , , , , , , , and 39 other author(s). ISSCC, page 204-206. IEEE, (2018)