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A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS.

J. Plouchart, M. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakhani, S. Yaldiz, L. Pileggi, R. Harjani, S. Reynolds, J. Tierno, and D. Friedman. CICC, page 1-4. IEEE, (2012)

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Humberto Jorge José

Pietro Tierno

Nadine José Gonzalez

Jose A C Broekaert

José Teixeira

Other publications of authors with the same name

An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz.M. Singh, J. Tierno, A. Rylyakov, S. Rylov, and S. Nowick. IEEE Trans. Very Large Scale Integr. Syst., 18 (7): 1043-1056 (2010)Asynchronous Parallel Prefix Computation.R. Manohar, and J. Tierno. IEEE Trans. Computers, 47 (11): 1244-1252 (1998)Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications.A. Rylyakov, J. Tierno, H. Ainspan, J. Plouchart, J. Bulzacchelli, Z. Deniz, and D. Friedman. ISSCC, page 94-95. IEEE, (2009)Asynchronous Circuits and Systems in Superconducting RSFQ Digital Technology.Z. Deng, S. Whiteley, T. Duzer, and J. Tierno. ASYNC, page 274-. IEEE Computer Society, (1998)Low-energy asynchronous memory design.J. Tierno, and A. Martin. ASYNC, page 176-185. IEEE, (1994)A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS.J. Plouchart, M. Sanduleanu, Z. Deniz, T. Beukema, S. Reynolds, B. Parker, M. Beakes, J. Tierno, and D. Friedman. CICC, page 1-4. IEEE, (2012)A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS.A. Rylyakov, J. Tierno, D. Turker, J. Plouchart, H. Ainspan, and D. Friedman. ISSCC, page 516-517. IEEE, (2008)A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing.B. Sadhu, M. Ferriss, A. Natarajan, S. Yaldiz, J. Plouchart, A. Rylyakov, A. Valdes-Garcia, B. Parker, A. Babakhani, S. Reynolds and 5 other author(s). IEEE J. Solid State Circuits, 48 (5): 1138-1150 (2013)Integrated transversal equalizers in high-speed fiber-optic systems.H. Wu, J. Tierno, P. Pepeljugoski, J. Schaub, S. Gowda, J. Kash, and A. Hajimiri. IEEE J. Solid State Circuits, 38 (12): 2131-2137 (2003)A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.T. Dickson, Y. Liu, S. Rylov, A. Agrawal, S. Kim, P. Hsieh, J. Bulzacchelli, M. Ferriss, H. Ainspan, A. Rylyakov and 7 other author(s). IEEE J. Solid State Circuits, 50 (8): 1917-1931 (2015)

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Disambiguation of "Tierno, José A."

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A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS.

Please choose a person to relate this publication to

Humberto Jorge José

Pietro Tierno

Nadine José Gonzalez

Jose A C Broekaert

José Teixeira

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Tierno, José A."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS.

Please choose a person to relate this publication to

Humberto Jorge José

Pietro Tierno

Nadine José Gonzalez

Jose A C Broekaert

José Teixeira

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS.