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A 195mW / 55mW dual-path receiver AFE for multistandard 8.5-to-11.5 Gb/s serial links in 40nm CMOS.

, , , , , , , , and . ISSCC, page 34-35. IEEE, (2013)

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A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2013)An 8.5-11.5-Gbps SONET Transceiver With Referenceless Frequency Acquisition., , , , , , and . IEEE J. Solid State Circuits, 48 (8): 1875-1884 (2013)A 60GHz 144-element phased-array transceiver with 51dBm maximum EIRP and ±60° beam steering for backhaul application., , , , , , , , , and 30 other author(s). ISSCC, page 66-68. IEEE, (2018)Asychnronous sampling based hybrid equalizer., and . ISCAS, page 1-4. IEEE, (2017)An 8.5-11.5Gbps SONET transceiver with referenceless frequency acquisition., , , , and . CICC, page 1-4. IEEE, (2012)A Fully Integrated 10-Gb/s Receiver With Adaptive Optical Dispersion Equalizer in 0.13-µm CMOS., , , , , , and . IEEE J. Solid State Circuits, 42 (4): 872-880 (2007)A 3.8 mW/Gbps quad-channel 8.5-13 Gbps serial link with a 5-tap DFE and a 4-tap transmit FFE in 28 nm CMOS., , , , , , , , , and 3 other author(s). VLSIC, page 348-. IEEE, (2015)A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 51 (4): 881-892 (2016)A low-power CMOS 155 Mb/s transceiver for SONET/SDH over co-ax and fibre., , , , , and . CICC, page 127-130. IEEE, (2001)An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology., , , , , , , , , and 12 other author(s). ISSCC, page 120-122. IEEE, (2022)