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Disambiguation of "Muller, Olivier"

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ASIP-based multiprocessor SoC design for simple and double binary turbo decoding.

, , and . DATE, page 1330-1335. European Design and Automation Association, Leuven, Belgium, (2006)

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Eduard Olivier

Lucien Olivier

Margarete Olivier

Thomas Olivier

Olivier Blanchard

 

Other publications of authors with the same name

Message-Oriented Devices on FPGAs., , , and . RSP, page 8-14. IEEE, (2018)Hardware Context Switch-based Cryptographic Accelerator for Handling Multiple Streams., , , , and . ACM Trans. Reconfigurable Technol. Syst., 14 (3): 14:1-14:25 (2021)Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration., , and . RSP, page 64-70. IEEE, (2021)A Fast and Autonomous HLS Methodology for Hardware Accelerator Generation under Resource Constraints., , and . DSD, page 201-208. IEEE Computer Society, (2013)On-board non-regression test of HLS tools targeting FPGA., , , , and . RSP, page 41-47. IEEE, (2016)(System)Verilog to Chisel Translation for Faster Hardware Design., , , , and . RSP, page 1-7. IEEE, (2020)Efficient Decompression of Binary Encoded Balanced Ternary Sequences., , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (8): 1962-1966 (2019)A Chisel Framework for Flexible Design Space Exploration through a Functional Approach., , and . CoRR, (2023)Can Knowledge Transfer Techniques Compensate for the Limited Myocardial Infarction Data by Leveraging Hæmodynamics? An in silico Study., , , , , , and . AIME, volume 13897 of Lecture Notes in Computer Science, page 218-228. Springer, (2023)Chisel Usecase: Designing General Matrix Multiply for FPGA., , and . ARC, volume 12083 of Lecture Notes in Computer Science, page 61-72. Springer, (2020)