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Power Estimation of Embedded Multiplier Blocks in FPGAs., and . IEEE Trans. Very Large Scale Integr. Syst., 18 (5): 835-839 (2010)Witelo: Automated generation and timing characterization of distributed-control macroblocks for high-performance FPGA designs., , and . Integr., (2019)Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs., , , , and . Int. J. Reconfigurable Comput., (2009)Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes., , , , , and . J. Syst. Archit., 60 (7): 579-591 (2014)Adding Value to TCP/IP Based Information exchange Security by Specialized Hardware., , and . SECURWARE, page 145-150. IEEE Computer Society, (2007)Architectural synthesis of DSP circuits under simultaneous error and time constraints., and . VLSI-SoC, page 322-327. IEEE, (2010)Precision-wise architectural synthesis of DSP circuits., and . EUSIPCO, page 562-566. IEEE, (2010)A TCP/IP Fragmentation Monitoring Core For Intrusion Prevention., , and . ERSA, page 227-230. CSREA Press, (2007)On interval methods applied to robot reliability quantification., and . Reliab. Eng. Syst. Saf., 70 (3): 291-303 (2000)Binary Division Power Models for High-Level Power Estimation of FPGA-Based DSP Circuits., , and . IEEE Trans. Ind. Informatics, 10 (1): 393-398 (2014)