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Distributed memory architecture for high-level synthesis of embedded controllers from Erlang.

, , , and . Erlang Workshop, page 13-19. ACM, (2017)

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Distributed memory architecture for high-level synthesis of embedded controllers from Erlang., , , and . Erlang Workshop, page 13-19. ACM, (2017)Synthesis of Full Hardware Implementation of RTOS-Based Systems., , , and . RSP, page 1-7. IEEE, (2018)Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing., , , , , , , , , and 2 other author(s). IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 97-A (12): 2518-2529 (2014)Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis., , , , , , , , , and 2 other author(s). ASP-DAC, page 14-15. IEEE, (2015)Binary synthesis implementing external interrupt handler as independent module., , , , and . RSP, page 92-98. ACM, (2017)Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture., , , , , , , , , and 4 other author(s). IEEE Embed. Syst. Lett., 10 (4): 119-122 (2018)High-Level Synthesis of Software Function Calls., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (12): 3556-3558 (2008)