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Disambiguation of "Elliott, Duncan G."

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Computational RAM: Implementing Processors in Memory.

, , , , and . IEEE Des. Test Comput., 16 (1): 32-41 (1999)

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Jonathan Elliott

Hazel Duncan

Elliott Brooks

Eeva Elliott

Duncan MacVicar

 

Other publications of authors with the same name

Design, evaluation and fault-tolerance analysis of stochastic FIR filters., , , and . Microelectron. Reliab., (2016)Frequency Synthesis Based on A Novel Differential Locking Mechanism., and . ISCAS, page 1-5. IEEE, (2018)High-Voltage CMOS Controller for Microfluidics., , , , and . IEEE Trans. Biomed. Circuits Syst., 3 (2): 89-96 (2009)Low-power static and dynamic high-voltage CMOS level-shifter circuits., , , , , , and . ISCAS, page 1946-1949. IEEE, (2008)Deeply Pipelined Digit-Serial LDPC Decoding., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (12): 2934-2944 (2012)Efficient Encoding and Termination of Low-Density Parity-Check Convolutional Codes., , , and . GLOBECOM, IEEE, (2006)Design and Characterization of a Multilevel DRAM., , , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (9): 1583-1596 (2011)Design of a 3-D fully depleted SOI computational RAM., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (3): 358-369 (2005)Jointly Designed Architecture-Aware LDPC Convolutional Codes and High-Throughput Parallel Encoders/Decoders., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (4): 836-849 (2010)Efficient Implementation of Low-Density Parity-Check Convolutional Code Encoders With Built-In Termination., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (11): 3628-3640 (2008)