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Disambiguation of "Shrivastava, Aviral"

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PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors.

, , , and . DATE, page 1264-1269. IEEE Computer Society, (2005)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Aviral Shrot

Ashish Shrivastava

Magan Bihari Shrivastava

Kailash Narain Shrivastava

 

Other publications of authors with the same name

Return Data Interleaving for Multi-Channel Embedded CMPs Systems., , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (7): 1351-1354 (2012)Automatic management of Software Programmable Memories in Many-core Architectures., , , , , and . IET Comput. Digit. Tech., 10 (6): 288-298 (2016)Cyclebite: Extracting Task Graphs From Unstructured Compute-Programs., , , , , and . IEEE Trans. Computers, 73 (1): 221-234 (January 2024)A run-time verification method with consideration of uncertainties for cyber-physical systems., , , , and . Microprocess. Microsystems, (2023)Partitioning techniques for partially protected caches in resource-constrained embedded systems., , , and . ACM Trans. Design Autom. Electr. Syst., 15 (4): 30:1-30:30 (2010)GiPH: Generalizable Placement Learning for Adaptive Heterogeneous Computing., , , , , , , , and . CoRR, (2023)Introduction to the Special Issue on Time for CPS (TCPS)., and . ACM Trans. Cyber Phys. Syst., 5 (2): 12:1-12:2 (2021)Crossroads+: A Time-aware Approach for Intersection Management of Connected Autonomous Vehicles., , , and . ACM Trans. Cyber Phys. Syst., 4 (2): 20:1-20:28 (2020)Static Analysis of Register File Vulnerability., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (4): 607-616 (2011)Blame-Free Motion Planning in Hybrid Traffic., , and . IEEE Trans. Intell. Veh., 9 (1): 259-268 (January 2024)