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PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors.

, , , and . DATE, page 1264-1269. IEEE Computer Society, (2005)

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R-Kleene: A High-Performance Divide-and-Conquer Algorithm for the All-Pair Shortest Path for Densely Connected Networks., and . Algorithmica, 47 (2): 203-213 (2007)An Approach to Combine Predicated/Speculative Execution for Programs with Unpredictable Branches., , and . IFIP PACT, volume A-50 of IFIP Transactions, page 147-156. North-Holland, (1994)Measuring the Parallelism Available for Very Long Instruction Word Architectures., and . IEEE Trans. Computers, 33 (11): 968-976 (1984)Uniform Parallelism Exploitation in Ordinary Programs.. ICPP, page 614-618. IEEE Computer Society Press, (1985)Applying an Abstract Data Structure Description Approach to Parallelizing Scientific Pointer Programs., , and . ICPP (2), page 100-104. CRC Press, (1992)Using Hardware Counters to Predict Vectorization., , , , , and . LCPC, volume 11403 of Lecture Notes in Computer Science, page 3-16. Springer, (2017)Adapting cache line size to application behavior., , , , and . International Conference on Supercomputing, page 145-154. ACM, (1999)Abstract Description of Pointer Data Structures: An Approach for Improving the Analysis and Optimization of Imperative Programs., , and . LOPLAS, 1 (3): 243-260 (1992)Comparative architectural characterization of SPEC CPU2000 and CPU2006 benchmarks on the intel® CoreTM 2 Duo processor., , , , , , and . ICSAMOS, page 132-141. IEEE, (2008)Cache-aware partitioning of multi-dimensional iteration spaces., , , , and . SYSTOR, page 15. ACM, (2009)